Most output buffers comprise a control function to adjust a maximum slew rate of the output voltage in response to a voltage step applied at the input to the buffer.
The electrical diagram for a conventional output buffer 100 according to the state of the art is presented with reference to FIG. 1. This output buffer 100 is powered by a power supply VDC and it comprises an input 101 onto which an input signal 1011 is applied and an output 102 on which the maximum slew rate can be measured starting from the voltage of the output signal 1021 measured at the terminals of the capacitor C1 of a load (placed between the output potential 102 and the ground 104).
This output buffer 100 comprises an output stage 103 that itself comprises a first PMOS type of output transistor 1031 and a second NMOS type of output transistor 1032.
The output buffer 100 also includes a block 105 comprising eight transistors M10 to M17 (block 105 being powered by the power supply voltage VDC). This processing block 105 controls the maximum slew rate of the output signal 103. It uses the input signal 1011 to output the control for the first gate 10311 and the second gate 10321 of the first and second transistors 1031 and 1032 of the output stage 103.
FIGS. 2A to 2E present curves of the output voltage 1021 (FIG. 2B), the first gate voltage 10312 (FIG. 2D), the second gate voltage 10322 (FIG. 2C) and the drain current 106 (FIG. 2E) from the transistor M17 of the output buffer in FIG. 1 in response to an input signal 1011 in the form of a voltage step changing from 0 to VDC (FIG. 2A), as a function of time t (in milliseconds).
The voltage curves are shown in V and the current 106 in mA. The time steps of the curves in FIGS. 2A to 2D are the same as the time steps of the curve in FIG. 2E.
The voltage step (FIG. 2A) from 0 to VDC applied at the input 101 corresponds to a transition from a logical 0 to a logical 1.
Starting from such a transition from a logical 0 to a logical 1 at the input signal 1011, the transistor M11 becomes conducting and the second gate voltage 10322 drops quickly from VDC to 0 (as shown in FIG. 2C).
Due to the fact that the output voltage 1021 is zero before the transition, the transistor M17 is conducting at the time of the transition. Thus, the sum of the internal resistances of transistors M17 and M16 forms a voltage divider bridge with the internal resistance of transistor M14, to reduce the drop in the first gate voltage 10312 (plateau in FIG. 2D) and reduce the increase in the drain current from the first output transistor 1031. The current in the divider bridge is shown by the drain current 106 from transistor M17 (FIG. 2E).
The result is to limit the slew rate of the output signal 1021.
When the output voltage level becomes sufficiently high, the transistor M17 is cut off and the drain current 106 from transistor M17 drops to zero (FIG. 2E). The signal 10311 applied to the gate of the output transistor 1031 changes to zero.
FIGS. 3A to 3E present curves showing the output voltage 1021 (FIG. 3B), the first gate voltage 10312 (FIG. 3D), the second gate voltage 10322 (FIG. 3C) and the drain current (FIG. 3E) from transistor M10 of the output buffer in FIG. 1 in response to an input signal 1011 in the form of a voltage step changing from 5 V (VDC) to 0 V (FIG. 3A), as a function of time t (in milliseconds).
In these curves, the voltage is shown in V and the current 107 is shown in mA. The time step of the curves in FIG. 3A to 3D is the same as for the curve in FIG. 3E.
The voltage step (FIG. 3A) from VDC equal to 0 applied to input 101 corresponds to a transition from a logical 1 to a logical 0.
Starting from such a transition from a logical 1 to a logical 0 at the input signal 1011, the transistor M15 becomes conducting and the first gate voltage 10312 rises quickly from 0 to VDC (as shown by FIG. 3D).
Due to the fact that the output voltage 1021 is equal to VDC before the transition, the transistor M10 becomes conducting at the time of the transition. Thus, the sum of the internal resistances of transistors M10 and M12 forms a voltage divider bridge with the internal resistance of transistor M13 that reduces the increase in the second gate voltage 10322 (plateau in FIG. 3C) and reduces the increase in the drain current from the second output transistor 1032. The current in the divider bridge is shown by the drain current 107 from transistor M10 (FIG. 3E).
The consequence is to limit the slew rate of the output signal 1021.
When the output voltage level reaches a sufficient value, the transistor M10 is cut off and the drain current 107 from transistor M10 drops to 0 (FIG. 3E). The signal 10322 applied to the gate of the output transistor 1032 changes to 1.
FIGS. 4A and 4B present curves 41, 42, 43, 44, 45, 46 and 47 showing the output voltage 1021 (FIG. 4B) from the output buffer 100 in response to an input signal 1011 in the form of a voltage step from 0 to VDC (FIG. 4A) for capacitances C1 equal to 0 pF, 50 pF, 100 pF, 150 pF, 200 pF, 250 pF and 300 pF respectively, as a function of time t (in milliseconds).
Voltage curves are shown in V. The time step of the curve in FIG. 3A is the same as the time step of the curve in FIG. 3B.
When the capacitance C1 increases, the divider bridge formed by the sum of the internal resistances of transistors M17 and M16 and by the internal resistance of transistor M14 limits the drop of the first gate voltage 10312 and the increase in the drain current from the first control transistor 1031, regardless of the value of C1.
When the capacitance C1 increases, the divider bridge formed by the sum of internal resistances of transistors M10 and M12 and by the internal resistance of transistor M13 limits the increase in the second gate voltage 10322 and the increase in the drain current from the second control transistor 1032 regardless of the value of C1.
Note that the following expression is true during a transition from 0 to VDC:Voutput=Idp·t/C1  (1)
where Voutput is the output voltage 1021, Idp is the drain current from the first control transistor 1031 and t is time.
The voltage Vgs applied on the gate of transistor 1031 in the output stage only depends on the divider bridge formed by transistors M16, M17 and M14.
The following expression is true during a transition from VDC to 0 takes place:Voutput=Idn·t/C1  (2)
where Idn is the drain current from the second control transistor 1032.
The drain current Id from a transistor is given by the following expression:Id=K·W/L·(Vgs−Vt)  (3)
where K and Vt are constants that depend on the manufacturing process of the transistor, Vgs is the voltage between the gate and the source of the transistor and W and L are the width and length respectively of the transistor channel.
The voltage Vgs applied to the gate of transistor 1032 in the output stage depends only on the divider bridge formed by transistors M10, M12 and M13.
Thus, relations (1), (2) and (3) show that the maximum slew rate of the output voltage 1021 depends on the capacitance C1 of the load at the output from the buffer 100 (as shown in FIG. 4B) and also depends on the parameters of the process for manufacturing of the first control transistor 1031 and the second control transistor 1032.
This dependence of the output voltage on the load capacitance C1 is a problem when making an output buffer.
In particular as shown in FIG. 4B, when the value of the load capacitance at the output is low, the maximum slew rate of the output signal is high, which generates a high noise level through the output buffer 100.
This high noise level can disturb operation of other devices around the periphery of the output buffer 100. This is particularly annoying for example for onboard electronics, and is unfavourable for EMC (ElectroMagnetic Compatibility).